1.2product block diagram4
2.1wifi rf specification5
2.2sleep state management6
4.1 operating & storage conditions10
4.2 recommended reflow profile10
5.1 blister packaging11
0. revision history
the qca4004 is a single chip 1x1 802.11b/g/n mimo solution optimized for low-power embedded applications with single-stream capability for both transmit and receive. frame aggregation, reduced inter-frame spacing (rifs), and half guard intervals provide improved throughput on the link. additional 802.11n performance optimization, such as 802.11n frame aggregation (a-mpdu and a-msdu), is provided by drivers that support sdio bus transaction bundling (a form of bus aggregation) and low-overhead host assisted buffering (rx a-msdu and a-mpdu). these techniques can improve the performance and efficiency of applications involving large bulk data transfers (for example, file transfers or high-resolution video streaming). the typical data path consists of the host interface, mailbox dma, ahb, memory controller, mac, bb, and radio. the cpu drives the control path via register and memory access. external interfaces include usb lpm or spi slave, reference clock, and front-end components, as well as optional connections such as uart, spi/i2c, gpio, jtag. see the “system block diagram”
1.2 product block diagram
1.3 product features
◆ all-cmos ieee 802.11b/g/n 1x1 single-chip
◆ support tcp/udp ip protocol
◆ support smartconfig
◆ usb 2.0 at 480 mbps using an integrated controller and phy
◆ extensive hardware support for wlan coexistence through lpc message passing
◆ power and clock management for extended battery life
◆ green-tx power saving
◆ low-power listen mode and radio retention for reduced receive power consumption and sleep current
◆ support for transmit beam formee (txbfee)
◆ integrated pa, lna minimizing external component count
◆ optional external pa, lna support
◆ data rates of up to 54 mbps for 802.11g and 72.2 for 802.11n ht20, 150 mbps for ht40
◆ advanced power management to minimize standby, sleep and active power
◆ security support for wps, wpa2, wpa, wap and protected management frames
◆ block ack
◆ gpio/pwm/uart for console support
◆ jtag-based processor debugging supported
2. general specification
2.1 wifi rf specifications
3.3vdc ±10% supply voltage
wifi: uart / spi
802.11b: cck(11, 5.5mbps), qpsk(2mbps), bpsk(1mbps),
802.11 g/n: ofdm
phy data rates
802.11b: 11,5.5,2,1 mbps
802.11g: 54,48,36,24,18,12,9,6 mbps
802.11n: up to 150mbps
transmit output power
802.11b@ 1mbps 15±2dbm
802.11n@65mbps 15±2dbm (mcs 0_ht20)
13±2dbm (mcs 7_ht20)
15±2dbm (mcs 0_ht40)
13±2dbm (mcs 7_ht40)
802.11b /11mbps : evm≦-9db
802.11g /54mbps : evm≦-27db
802.11n /mcs 7 : evm≦-28db
mcs 0 -83±1dbm
mcs 1 -82±1dbm
mcs 2 -80±1dbm
mcs 3 -78±1dbm
mcs 4 -75±1dbm
mcs 5 -71±1dbm
mcs 6 -69±1dbm
mcs 7 -67±1dbm
11: (ch. 1-11) – united states(north america)
13: (ch. 1-13) – europe
14: (ch. 1-14) – japan
media access control
wifi: csma/ca with ack
wifi: ad-hoc mode (peer-to-peer )
wifi: wps, wpa2, wpa, wap
android /linux/ win ce /ios /xp/win7
2.2 sleep state management
chip_pwd_l pin assertion immediately brings the chip to this state.
sleep clock is disabled.
no state is preserved.
only the sleep clock is operating.
the crystal or oscillator is disabled.
any wakeup events (mac, host, lf timer, gpio interrupt) force a transition to wakeup.
all internal states are maintained.
the system transitions from sleep/off states to on.
the high frequency clock is gated off as the oscillator is brought up and the pll is enabled.
wakeup duration is usually 2 ms.
the high speed clock is operational and sent to each block enabled by the clock control register.
lower-level clock gating is implemented at the block level, including the cpu, which can be gated off using waiti instructions while the system is on. no cpu, host, or wlan activities go to sleep.
2.3 power consumption (unit: ma)
power on (standby)
11n mcs0 tx
11n mcs7 tx
11g 6m tx
11g 54m tx
11b cck1m tx
11b cck11m tx
11n mcs0 tx
11n mcs7 tx
3. mechanical specification
3.1 outline drawing (unit: ±0.15mm)
3.2 pin assignment
4. environmental requirements
4.1 operating& storage conditions
temperature: 0°c to +55°c
relative humidity: 10-90% (non-condensing)
temperature: -40°c to +80°c (non-operating)
relative humidity: 5-90% (non-condensing)
4.2 recommended reflow profile
referred to ipc/jedec standard.
peak temperature : <250°c
number of times : ≤2 times
4.3 patch wifi modules installed before the notice:
wifi module installed note:
1. please press 1 : 1 and then expand outward proportion to 0.7 mm, 0.12 mm thickness when open a stencil
2. take and use the wifi module, please insure the electrostatic protective measures.
3. reflow soldering temperature should be according to the customer the main size of the products, such as the temperature set at 250 + 5 ℃ for the mid motherboard.
about the module packaging, storage and use of matters needing attention are as follows:
1. the module of the reel and storage life of vacuum packing: 1). shelf life: 8 months, storage environment conditions: temperature in: < 40 ℃, relative humidity: < 90% r.h.
2. the module vacuum packing once opened, time limit of the assembly:
card: 1) check the humidity display value should be less than 30% (in blue), such as: 30% ~ 40% (pink), or greater than 40% (red) the module have been moisture absorption.
2.) factory environmental temperature humidity control: ≦ 30% ℃, ≦ 60% r.h..
3). once opened, the workshop the preservation of life for 168 hours.
3. once opened, such as when not used up within 168 hours:
1). the module must be again to remove the module moisture absorption.
2). the baking temperature: 125 ℃, 8 hours.
3.) after baking, put the right amount of desiccant to seal packages.